FIELD OF THE INVENTION
The invention relates to a method for fabricating a semiconductor structure in an integrated circuit, in particular a method for fabricating a hard mask and a method for removing the hard mask.
Silicon oxides are among the most frequently used materials in semiconductor technology. Various types of silicon oxides (glasses) are known which differ in terms of their composition, their properties and their fabrication, for example thermal and deposited oxides, TEOS, and doped oxides. They are used as insulation materials in many cases. A further important application is their use as a hard mask during the etching of layers lying at a deeper level. A hard mask of this type is removed again after the etching process.
A photolithographic process is required to produce the hard mask. In order to reduce pattern transfer errors in the course of this, it is possible to apply an antireflection layer (ARC) to the hard mask layer, for which purpose a plasma-enhanced deposition process is usually used. Customary methods provide for the hard mask layer composed of a silicon oxide to be applied in the vacuum chamber of a first installation and for the antireflection layer then to be applied in a second installation.
After the patterning process, the hard mask composed of silicon oxide should be removed wet-chemically as quickly as possible and usually selectively with respect to other layers that are present (for example thermal silicon oxide layers and silicon nitride layers). This requires a high, numerically accurately known etching rate for the hard mask. As a result of the effect of the plasma-enhanced deposition process for the antireflection layer on the exposed silicon oxide layer, however, the etching rate of the latter is reduced in an uncontrolled manner. The change in the etching rate can be attributed to chemical and physical layer modifications due to the subsequent plasma deposition. Since the etching rate of the hard mask layer cannot adequately be controlled, under manufacturing conditions the hard mask is not removed with a fixed process time, rather the process time is determined in a separate precursor test for a certain number of wafers (that is to say a batch). An individual etching time is established in this way for each batch. It is only by this time-consuming and cost-intensive procedure that an excessively high erosion of other layers present on the wafer can be avoided.
One example of the use of a hard mask made of doped silicon oxide with a superior antireflection layer is the etching of capacitor trenches in a silicon substrate, in particular for one-transistor memory cells. In the case of the etching process, an intermediate layer composed of thermal silicon oxide and/or silicon nitride is generally disposed directly on the substrate surface and must not be attacked, or may be attacked only slightly, during the removal of the hard mask after the trench etching. It may be expedient to etch the intermediate layer back horizontally by a defined amount (so-called pull back), for example in order to enable the trench to be better able to be filled. According to a known method, in order to remove the silicon oxide-based hard mask layers, mixtures containing H.sub.2 SO.sub.4 /HF are used here at approximately 60.degree. C on a spin etcher. The selectivity of the erosion of a doped glass layer with 4% by weight of boron with respect to the erosion of a thermal silicon oxide layer that is likewise situated on the wafer is approximately 35:1 in this case. In order to prevent an impermissibly high erosion of the thermal oxide, from each batch one wafer is subjected separately to a preliminary process step for determining the etching rate. The entire batch is subsequently processed with the etching time resulting from the etching rate that has been determined in this way. This step preceding the actual etching process considerably reduces the wafer throughput. After the removal of the hard mask, in a further process step, the edges of the silicon nitride layer situated under the hard mask are etched back by isotropic etching using an HF/ethylene glycol mixture in another etching installation.
It is known to increase the wet etching rate of doped silicon oxide hard masks by increasing the dopant concentration of the layers. However, this reduces their layer stability in the etching process, that is to say the layers no longer satisfy the requirements Appertaining to their use as a mask.